1. Field
Methods and apparatuses consistent with exemplary embodiments relate to a semiconductor device, and more particularly, to a delay-locked look (DLL) circuit and an integrated circuit (IC) including the same.
2. Description of the Related Art
A DLL circuit controls a delay line so that a phase of an input clock signal matches phases of a feedback signal output through the delay line. In order to compensate for process, voltage, and temperature (PVT) variations, a master DLL circuit may detect a selection value corresponding to a lock state and provide the selection value to a slave DLL circuit. The slave DLL circuit may generate an internal clock signal by delaying the input clock signal by a target delay amount based on the selection value. Since the selection value changes according to PVT, the slave DLL circuit may constantly maintain a phase difference between the input clock signal and the internal clock signal by compensating for a change in the input clock signal according to PVT variations, based on the selection value.